![]() The MMC3 scanline counter is based entirely on PPU A12, triggered on a rising edge after the line has remained low for three falling edges of M2. No major behavioral differences are known, except for the IRQ counter. Three revisions are known to exist - MMC3A, MMC3B, and MMC3C. The MMC3 most commonly exists in a 44-pin TQFP package. Writing any value to this register will enable MMC3 interrupts. Writing any value to this register will disable MMC3 interrupts AND acknowledge any pending interrupts. Writing any value to this register clears the MMC3 IRQ counter immediately, and then reloads it at the NEXT rising edge of the PPU address, presumably at PPU cycle 260 of the current scanline. When the IRQ counter is zero (or a reload is requested through $C001), this value will be copied to the IRQ counter at the NEXT rising edge of the PPU address, presumably at PPU cycle 260 of the current scanline. This register specifies the IRQ counter reload value. Many emulators choose not to implement them as part of iNES Mapper 4 to avoid an incompatibility with the MMC6. Though these bits are functional on the MMC3, their main purpose is to write-protect save RAM during power-off. +- PRG RAM chip enable (0: disable 1: enable)ĭisabling PRG RAM through bit 7 causes reads from the PRG RAM region to return open bus. |+- Write protection (0: allow writes 1: deny writes) PRG RAM protect ($A001-$BFFF, odd) 7 bit 0 In the iNES and NES 2.0 formats, this can be identified through bit 3 of byte $06 of the header. This bit has no effect on cartridges with hardwired 4-screen VRAM. ![]() +- Nametable mirroring (0: vertical 1: horizontal) R0 and R1 ignore the bottom bit, as the value written still counts banks in 1KB units but odd numbered banks can't be selected. Some romhacks rely on an 8-bit extension of R6/7 for oversized PRG-ROM, but this is deliberately not supported by many emulators. R6 and R7 will ignore the top two bits, as the MMC3 has only 6 PRG ROM address lines. ++++-++++- New bank value, based on last value written to Bank select register (mentioned above) The MMC3 uses one map if bit 6 was cleared to 0 (value & $40 = $00) and another if set to 1 (value & $40 = $40).īecause the values in R6, R7, and $8000 are unspecified at power on, the reset vector must point into $E000-$FFFF, and code must initialize these before jumping out of $E000-$FFFF. (The lowest bit is ignored.)īit 6 of the last value written to $8000 swaps the PRG windows at $8000 and $C000. +- CHR A12 inversion (0: two 2 KB banks at $0000-$0FFF,ĢKB banks may only select even numbered CHR banks. |+- PRG ROM bank mode (0: $8000-$9FFF swappable, ||| 111: R7: Select 8 KB PRG ROM bank at $A000-$BFFF ||| +++- Specify which bank register to update on next write to Bank Data register These can be broken into two independent functional units: memory mapping ($8000, $8001, $A000, $A001) and scanline counting ($C000, $C001, $E000, $E001). The MMC3 has 4 pairs of registers at $8000-$9FFF, $A000-$BFFF, $C000-$DFFF, and $E000-$FFFF - even addresses ($8000, $8002, etc.) select the low register and odd addresses ($8001, $8003, etc.) select the high register in each pair. PPU $1C00-$1FFF (or $0C00-$0FFF): 1 KB switchable CHR bank.CPU $E000-$FFFF: 8 KB PRG ROM bank, fixed to the last bank.CPU $C000-$DFFF (or $8000-$9FFF): 8 KB PRG ROM bank, fixed to the second-last bank.CPU $A000-$BFFF: 8 KB switchable PRG ROM bank.CPU $8000-$9FFF (or $C000-$DFFF): 8 KB switchable PRG ROM bank.CPU $6000-$7FFF: 8 KB PRG RAM bank (optional).
0 Comments
Leave a Reply. |
AuthorWrite something about yourself. No need to be fancy, just an overview. ArchivesCategories |